Method for decoding data sequence encoded with aid of binary convolution code

ABSTRACT

A data sequence consisting of K information bits that has been encoded with the help of a binary convolution code is decoded using a MaxLogMAP algorithm. In a first calculation operation, metric values are calculated accurately in a forwards and backwards direction in a trellis diagram and only some of the values are stored in a memory as interpolation points for an additional calculation operation. The additional calculation operation uses the interpolation points to accurately calculate the metric values that lie between the interpolation points of the first calculation operation. Soft output values are accurately determined for decoding after n operations.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and hereby claims priority to German PatentApplication No. 102 13882.6 and European Patent Application No. 020 07030.6, both filed on Mar. 27, 2002, the contents of which are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for decoding a data sequencewhich consists of K information bits and has been encoded with the aidof a binary convolutional code, using a MaxLogMAP algorithm.

2. Description of the Related Art

Voice channels and data channels of a radio communications system, whichis designed to operate to the GSM/EDGE mobile radio communicationsstandard for example, use binary convolutional codes for data coding anddata decoding. A preferred algorithm for what is known as “softinput/soft output decoding” is the known “symbol-by-symbollog-likelihood maximum a posteriori probability” algorithm (LogMAPalgorithm), which is generally implemented with the aid of a maximumapproximation (MaxLogMAP algorithm).

The basic MAP algorithm is described, for example, in the publication“Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate”, L.R. Bahl et al., IEEE Transactions on Information Theory, pp. 284–287,March 1974. The MaxLogMAP algorithm can be found in the publication“Iterative Decoding of Binary Block and Convolutional Codes”, J.Hagenauer et al., IEEE Transactions on Information Theory, vol. 42, no.2, pp. 429–445, March 1996.

A window MaxLogMAP algorithm implemented with the aid of what is knownas a “sliding window” (decoding window) is described in the publication“An Intuitive Justification and a Simplified Implementation of the MAPDecoder for Convolutional Codes”, A. J. Viterbi, IEEE Journal onSelected Areas in Communications, vol. 16, no.2, pp. 260–264, February1998.

The basis for decoding a data sequence encoded with the aid of a binaryconvolutional code is the binary trellis diagram. One segment of thetrellis diagram belonging to one information bit of the data sequencedetects all possible combinations of m (convolutional code memorylength) preceded information bits as 2^(m) initial states. Furthermore,all ensuing “conversions” (codings) of the information bit are detectedas 2^((m+1)) state transitions, and resulting 2^(m) target states aredetected as initial states for the next consecutive information bit.Here an information bit sequence corresponds to a specific path withinthe trellis diagram, a sequence of the most probable information bits inthe trellis diagram being established with the aid of the MaxLogMAPalgorithm.

When the MaxLogMAP algorithm is implemented, a distinction essentiallyhas to be made between a systolic implementation and aprocessor-oriented implementation.

With the systolic implementation the aim is to achieve as high a degreeof parallelism as possible of decoding steps throughout the trellisdiagram. This implementation is used with extremely high data throughputrequirements of up to 50 Gbit/s.

Processor-oriented implementation is suitable for moderate datathroughput requirements of a few Mbit/s using low-cost hardware.

For both implementations it is assumed that, for large data sequencestransmitted block-by-block, decoding can be usefully implemented onlywith the aid of a decoding window.

For reasons of data throughput and hardware cost the window MaxLogMAPalgorithm is generally used for decoding.

Decoding results (soft output values) which are, by way of comparison,obtained using a MaxLogMAP algorithm without a decoding window may bemore precise, but expensive hardware and memories are required for thispurpose.

An alternative to the MaxLogMAP algorithm, based on a block errorprobability with a given signal-to-noise ratio, is provided by the “softoutput Viterbi algorithm” (SOVA) described in DE 39 10 739 C3 and DE 4224 214 C2. However, the SOVA algorithm has a smaller correlation betweendecoding errors and soft output values formed than the MaxLogMAPalgorithm.

SUMMARY OF THE INVENTION

An object of the present invention is to carry out a decoding of a datasequence encoded with the aid of a binary convolutional code, using aMaxLogMAP algorithm, in such a manner that precise soft output valuesare formed as decoding results with inexpensive hardware.

A method according to the invention may be a processor-orientedimplementation of the MaxLogMAP algorithm.

As a result of the memory cascading according to the invention on theone hand and the use of interpolation nodes for metrics calculation onthe other hand, the MaxLogMAP algorithm can be efficiently integrated onexactly one application-specific module (ASIC).

The non-use of a decoding window must not entail a loss of accuracy ofthe decoding results.

According to the invention the metrics values are calculatedproductively in a first calculation operation and reproductively infurther calculation operations based on the stored interpolation nodes.

The memory cascading according to the invention enables an optimal datathroughput to be achieved.

The method according to the invention saves memory space and thereforearea on an ASIC module. The area saved is therefore available forfurther signal processing algorithms, which means that additionalalgorithms can be implemented in the ASIC module.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of the preferred embodiments, taken in conjunction with theaccompanying drawings of which:

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of an exemplary embodiment, taken in conjunction with theaccompanying drawings of which:

FIG. 1 is a diagrammatic representation of a MaxLogMAP algorithm for theprecision calculation of soft output values according to the relatedart,

FIG. 2 is a diagrammatic representation of a window MaxLogMAP algorithmfor the calculation of soft output values according to the related art,

FIG. 3 is a diagrammatic representation of a MaxLogMAP algorithmaccording to the invention for the precision calculation of soft outputvalues, and

FIG. 4 is a diagrammatic representation for an example of the metricsvalue calculation and storage according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to like elementsthroughout.

FIG. 1 is a diagrammatic representation of a MaxLogMAP algorithm for theprecision calculation of soft output values according to the relatedart.

The MaxLogMAP algorithm is used to decode a data sequence which consistsof K information bits and has been encoded with the aid of a binaryconvolutional code.

On a trellis diagram TREL, starting at a trellis segment T1, alphametrics values Mα-calc-store are calculated and stored for everyindividual trellis segment TSN as logarithmic transition probabilities.At the same time, in parallel therewith, starting at a trellis segmentT2, beta metrics values M-calc-store are calculated and stored for everyindividual trellis segment TSN.

The two calculations pass each other at a trellis segment TSM, adecision process being carried out from this time onwards for thepurpose of calculating a soft output value, i.e. an information bit ofthe data sequence is decoded. When that happens, in the course of a“forward decision process” FDP, after the trellis segment TSM has beenpassed, currently calculated alpha metrics values Mα-calc are used withthe previously calculated and stored beta metrics values Mβcalc-store tocalculate the soft output value.

This procedure takes place at the same time in a “backward decisionprocess” BDP, wherein currently calculated beta metrics values Mβ-calcare used with the previously calculated and stored alpha metrics valuesMα-calc-store to calculate the soft output value.

The following reference characters are used below:

-   K number of information bits,-   s state of a convolutional code decoding,-   m code memory length,-   T required number of trellis segments, where T=K+m, and-   π length of a transient phase, where π>5*m

With a word width w of a metrics memory and assuming that the respectivemetrics values are standardized, two metrics processors and a total of2·K/2·w·2^(m) memory locations are required for this implementation ofthe MaxLogMAP algorithm. The data throughput achieved is as follows:

${\frac{1}{t_{segment} \cdot 10^{6}}\left\lbrack {M\;{{bit}/s}} \right\rbrack},$where the above parameter t_(segment) is dependent on the moduletechnology (ASIC) used to implement the algorithm, on the memoryarchitecture and on the clock speed used with the ASIC module.

In the case of terminated codes, each calculation of the metrics valuesstarts from the assumption of an uneven probability distribution in atrellis segment having an initial state with a probability of 100%,while all further states have a probability of 0%.

In the case of what are known as “tailbiting codes” no initial state isknown at the outset. A transient phase of length π therefore has to beintroduced for both directions. Associated metrics values for thetransient phase are indicated as Mα-pre and Mβ-pre respectively.

FIG. 2 is a diagrammatic representation of a window MaxLogMAP algorithmfor the calculation of soft output values according to the related art.

The window MaxLogMAP algorithm, which is implemented with the aid of asliding decoding window, is used for long data sequences. The particularadvantage of the window MaxLogMAP algorithm is its efficientimplementation.

Similarly to FIG. 1, alpha metrics values Mα-calc are calculatedprecisely in a forward direction starting at a trellis segment T1. Bycontrast, beta metrics values Mβ-calc-1 of a first decoding window DP1and beta metrics values Mβ-calc-2 of a second decoding window DP2 areestimated.

If the two decoding windows DP1 and DP2 reach the right-hand edge of thetrellis diagram TREL, all the termination information is available. Thebeta metrics values Mβ-calc-1 and Mβ-calc-2 are calculated precisely,and the corresponding soft output values are formed.

Metrics values Mα-pre, Mβ-pre-1 and Mβ-pre-2 are again assigned to atransient phase.

The window MaxLogMAP algorithm is described in detail in theabove-mentioned publication “An Intuitive Justification and a SimplifiedImplementation of the MAP Decoder for Convolutional Codes”.

For this implementation, with a data throughput similar to that of FIG.1, in total ┌w/ψ┐+1 metrics processors and (1+θ)·ψ·w·2^(m) storagelocations are required,

where:

ψ is the number of trellis segments for which 2^(m) metrics are storedin each case, w is the size of the decoding window in trellis segments,and θ ∈ {0,1} is a parameter which is dependent on the module technology(ASIC) used to implement the algorithm, on the memory architecture andon the clock speed used with the ASIC module.

Especially where high speed channels have code rates close to one(generated with the aid of a points system), use of the decoding windowleads to unacceptable deteriorations in performance, however.

FIG. 3 is a diagrammatic representation of a MaxLogMAP algorithmaccording to the invention for the precision calculation of soft outputvalues.

Similarly to FIG. 1, alpha metrics values are again calculated in aforward direction and beta metrics values in a backward direction ofeach trellis segment TSN. However, now, in accordance with theinvention, only metrics values of a selected number of trellis segmentswhich act as interpolation nodes are selected and stored.

In a preferred embodiment they are stored in a memory divided intolevels in a cascaded manner.

The following reference characters are used below:

m code memory length, sm memory length shift of a feed-forwardterminated code (in the case of a recursively terminated code and in thecase of a tail- biting code sm = 0), K number of information bits, Trequired number of trellis segments, where T = K + m; π length of thetransient phase where π > 5*m, δ(1) memory depth of a first memory levelSP(1) for interpolation nodes of a first metrics value calculation, δ(n− 1) memory depth of an n − 1-th memory level SP(n − 1) forinterpolation nodes of an n − 1-th metrics value calculation, and δ(n)memory depth of an n-th memory level SP(n) for interpolation nodes of ann − 1-th metrics value calculation.

On the trellis diagram TREL, in a first operation, starting at a trellissegment T1, alpha metrics values Mα-calc(1) are calculated in a forwarddirection FDP and, starting at a trellis segment T2, beta metrics valuesMβ-calc(1) are calculated in a backward direction BDP for each one ofthe trellis segments TSN as logarithmic transition probabilities.

According to the invention, however, from the calculated metrics valuesMα-calc(1) and Mβ-calc(1) of the first operation, metrics valuesMα-calc-sel(1) and Mβ-calc-sel(1) of the first operation are each nowfiled in a first memory level SP(1) with a memory depth of δ(1) for aselection of K/δ(1) trellis segments acting as interpolation nodes.

In a second operation, on the basis of each pair of adjacentinterpolation nodes of the first operation, metrics values Mα-calc(2)and Mβ-calc(2) are calculated for the trellis segments TSN positionedbetween the respective interpolation nodes of the first operation.

As in the first operation, from the calculated metrics values Mα-calc(2)and Mβ-calc(2) of the second operation, for a selection of K/δ(1)/δ(2)trellis segments again acting as interpolation nodes the correspondingmetrics values Mα-calc-sel(2) and Mβ-calc-sel(2) of the second operationare filed in a second memory level SP(2) with a memory depth of δ(2).

This metrics value calculation based on the interpolation nodes of aprevious operation is accordingly continued both in a forward directionand in a backward direction. During this process, after the trellissegment TSM is passed, corresponding soft output values are formed,memory levels that are released being accordingly reused.

Here the decision process for the determination of the soft outputvalues is as described in FIG. 1. The individual memory levels arearranged in a mutually cascaded structure.

After n operations all soft output values are determined, the n-thmemory level having a memory depth of δ(n) with stored metrics values ofK/δ(1)/δ(2)/ . . . /δ(n) trellis segments or interpolation nodes.

Comparing this with the data throughput stated in FIG. 1 and FIG. 2, themethod according to the invention requires a total of 2·n metricsprocessors and

$\left( {\sum\limits_{i = 1}^{n}\;{\left( {1 + \theta_{i}} \right) \cdot \delta_{i}}} \right) \cdot w \cdot 2^{m}$storage locations.

The following applies:

${{\prod\limits_{i = 1}^{n}\;\delta_{i}} = K},{\theta_{i} \in \left\{ {0,1} \right\}},$according to the number of ASIC clock cycles required for one trellissegment and the number of ports available on the memories.

On the basis of existing implementations of the MaxLogMAP windowalgorithm, parameters can be deduced and can be used for a comparisonbetween the conventional implementations known from FIG. 1 and FIG. 2and the implementation according to the invention.

The results can be found in the following Table:

Logic “Area” [Kgates] Memory [Kbit] [Kgates] MaxLogMAP 101 1080 2300Window MaxLogMAP 233 138 500 Memory-cascaded 233 106 450 implementation

With the same data throughput and with no loss of accuracy in theMaxLogMAP algorithm as a result of the non-use of a decoding window,hardware costs for the memory-cascaded implementation according to theinvention are reduced by over 80% compared with the conventionalimplementation described in FIG. 1.

The following assumptions were made for this comparison:

-   an overhead resulting from soft input and soft output buffer at a    systems interface with    (R⁻¹+1)·w_(soft)·k·a_(memory)    -   where k=K generally applies but k=W+((n_(β)−1)*{overscore (0)})        may apply to implementation with decoding window; where R is        code rate, w_(soft) is word width of the soft values and        a_(memory) is unit area per memory bit,-   an overhead resulting from control module and interface:    A_(overhead).-   a metrics processor including scaling of the register bits:    A_(viterbi)(w)·f_(parallel)+2^((m+1))·w·a_(flipflop)-   where A_(viterbi) represents the Viterbi arithmetic for a given word    width w and a_(flipflop) represents the register unit area per bit,    f_(parallel) is the number of butterfly calculations made in an ASIC    clock cycle and can assume the following values: {1,2, . . . ,    2^((m−1))},-   a metrics word width w=16,-   a soft value word width w_(soft)=8,-   a memory bit area a_(memory)=2,-   a register bit area a_(flipflop)=10 units,-   a Viterbi arithmetic/butterfly A_(viterbi)=12500 units,-   an overhead A_(overhead)=50000 units.

The units correspond to a gate equivalent of a 0.18 μm ASIC module at aclock frequency of approx. 150 MHz.

Data from a parameter set relevant to the GSM/EDGE standard are comparedbelow:

code rate R = 1/6 memory length m = 6 block size K = 1000 decoderthroughput greater than 2 Mbit/s parallelism f_(parallel) = 1Configuration “Area” (@ 2.6 Mbit/s) [Kgates] Exact implementation 2metrics processors 2250 Window implementation 7 metrics processors 480(path fusion limit = 160) (1 + θ) metrics memory window also with softwith δ = 32, θ = 1 input and soft output 1 soft input and soft outputmemory memory with window Window implementation 6 metrics processors 500(path fusion limit = 160) (1 + θ) metrics memory with δ = 40, θ = 1 1soft input and soft output memory Window implementation 5 metricsprocessors 425 (path fusion limit = 160) (1 + θ) metrics memory with δ =54, θ = 0 1 soft input and soft output memory Memory-cascaded 6 metricsprocessors 450 implementation interpolation nodes memory at the 1^(st)level with δ₁ = 18; (1 + θ₂) * 2 interpolation nodes memory at the2^(nd) level with δ₂ = 8, θ₂ = 1; (1 + θ₃) * 2 metrics memories with δ₃= 7, θ₃ = 1; 1 soft input and soft output memory Memory-cascaded 6metrics processors 400 implementation 2 interpolation nodes memories atthe 1^(st) level with δ₁ = 18; (1 + θ₂) * 2 interpolation nodes memoryat the 2^(nd) level with δ₂ = 10, δ₁ = 10; θ₂ = 0; (1 + θ₃) * 2 metricsprocessors with δ₃ = 10, θ₃ = 0; 1 soft input and soft output memory

In the case of UMTS (W-CDMA) and with UTRAN TDD convolutional codes, thefollowing parameters are to be used for the convolutional decoding:

code rate R = 1/3 memory length m = 8 maximum block size K = 300 decoderthroughput greater than 2 Mbit/s parallelism f_(parallel) = 8Configuration “Area” (@ 3.125 Mbit/s) [Kgates] Exact implementation 2metrics processors 2891 Window implementation 6 metrics processors 1848with sliding window on soft input/ δ = 40, θ = 1 soft output memoryMemory-cascaded 4 metrics processors 1206 implementation δ₁ = 20, δ₂ =15 θ₁ = 0, θ₂ = 1

In the case of UMTS (W-CDMA) and with UTRAN TDD turbo codes a slightlyexpanded MaxLogMAP decoder can be used as part of the turbo-decoding.This means that, here too, memory-cascaded implementation can becompared with direct and window implementation:

code rate R = 1/3 memory length m = 3 maximum block size K = 5200decoder throughput greater than 2 Mbit/s parallelism f_(parallel) = 1/4Configuration “Area” (@ 3.125 Mbit/s) [Kgates] Exact implementation 2metrics processors 1727 Window implementation 6 metrics processors 159with sliding window also δ = 40, θ = 1 for soft input/soft output memoryMemory-cascaded 8 metrics processors 448 implementation δ₁ = 13; δ₂ =10, δ₃ = 8, δ₄ = 5 θ₁ = 0, θ_(i) = 1 for i = {2, 3, 4}

FIG. 4 shows an example of metrics value calculation and storageaccording to the invention.

In a first operation D1, alpha metrics values and beta metrics valuesare calculated. For each sixth trellis segment TSN=1, 7, 13, . . . , 73acting as interpolation point, 2^(m) calculated alpha metrics values arestored in a memory level SP(α1) and 2^(m) calculated beta metrics valuesare stored in a memory level SP(β1).

In a second operation D2, these metrics values are read out of thememory levels SP(α1) and SP(β1) and, for the trellis segments positionedbetween the interpolation nodes, the associated alpha metrics values andbeta metrics values are calculated precisely. Relevant trellis segmentsare again selected as interpolation nodes, and the associated metricsvalues are stored. Two memory levels SP(α2) and SP(α2′), and SP(β2)andSP(β2′), respectively, are indicated here by way of example.

In a third operation D3, the trellis segment TSM is reached from bothsides, and currently calculated 2^(m) beta metrics values with stored2^(m) alpha metrics values filed in the memory SP(α2) are used for thebackward decision process to determine soft output values. In exactlythe same way, currently calculated 2^(m) alpha metrics values withstored 2^(m) beta metrics values filed in the memory SP(β2) are used forthe forward decision process to determine soft output values.

After a total of n=3 operations Dn all the decisions valuesM_(decisions) were formed.

The invention has been described in detail with particular reference topreferred embodiments thereof and examples, but it will be understoodthat variations and modifications can be effected within the spirit andscope of the invention covered by the claims which may include thephrase “at least one of A, B and C” as an alternative expression thatmeans one or more of A, B and C may be used, contrary to the holding inSuperguide v. DIRECTV, 69 USPQ2d 1865 (Fed. Cir. 2004).

1. A method for decoding a data sequence of K information bits encodedwith aid of a binary convolutional code, comprising: calculating in afirst operation, on a trellis diagram having trellis segments, firstmetric values of all trellis segments for a forward direction and for abackward direction using a MaxLogMAP algorithm without a decodingwindow; selecting a first set of trellis segments as first interpolationnodes from the first operation; storing first associated metric valuesfor the first set of trellis segments in a first memory level;iteratively performing a number of n operations until the metric valuesfor the forward direction and for the backward direction meet in onetrellis segment, including: calculating in an i-th operation for 1<i≦n,i-th metric values of internodal trellis segments positioned between theinterpolation nodes of an i−1-th operation for the forward and thebackward directions using stored metric values of interpolation nodes ofthe i−1-th operation, selecting an i-th set of trellis segments as i-thinterpolation nodes from the i-th operation, and storing i-th associatedmetric values for the i-th set of trellis segments in an i-th memorylevel; and carrying out a decision process to calculate soft outputvalues for decoding.
 2. A method according to claim 1, furthercomprising: assigning a memory depth of δ1 for each direction of thefirst memory level, and wherein said storing of the first associatedmetric values in the first memory level uses each K/δ1-th trellissegment.
 3. A method according to claim 2, further comprising: assigninga memory depth of δi for each direction of the i-th memory level, andwherein said storing of the first associated metric values in the firstmemory level uses each K/δ1/ . . . /δi-th trellis segment.
 4. A methodaccording to claim 3, wherein a delayed decision phase is used incalculating the soft output values for terminated codes.
 5. A methodaccording to claim 4, wherein the decoding is carried out on a singleapplication-specific module.
 6. A method according to claim 3, whereinthe decoding is carried out on a single application-specific module. 7.A method according to claim 2, wherein a delayed decision phase is usedin calculating the soft output values for terminated codes.
 8. A methodaccording to claim 2, wherein the decoding is carried out on a singleapplication-specific module.
 9. A method according to claim 1, furthercomprising: assigning a memory depth of δi for each direction of thei-th memory level, and wherein said storing of the first associatedmetric values in the first memory level uses each K/δ1/ . . . /δi-thtrellis segment.
 10. A method according to claim 1, wherein a delayeddecision phase is used in calculating the soft output values forterminated codes.
 11. A method according to claim 1, wherein thedecoding is carried out on a single application-specific module.